IBM has unveiled what it calls the world’s first sub-1 nanometer chip technology, featuring a revolutionary transistor architecture at the 0.7 nanometer (7 angstrom) node. The achievement, announced on June 25, 2026, marks a landmark moment for the semiconductor industry, which has been grappling with the physical limits of traditional chip scaling for over a decade. IBM’s new “nanostack” architecture could extend Moore’s Law — the observation that the number of transistors on a chip doubles approximately every two years — for at least another decade.
What Is the Nanostack Architecture?
The nanostack is the industry’s first known three-dimensional, nanosheet-based transistor design. Rather than continuing to shrink transistors in two dimensions — the approach that has driven chip advancement for 50 years — IBM’s team decided to build upward. The architecture vertically stacks transistors in two layers on a silicon chip, dramatically increasing transistor density without requiring further horizontal shrinkage.
“It’s not just an incremental step,” says Jay Gambetta, the director of IBM Research, during the press conference announcing the breakthrough. “It’s a meaningful leap forward.” Within a decade, Gambetta expects, chips with nanostacking will be widely used in data centers, where their improved efficiency could help facilities better manage their energy consumption.
The Numbers: 100 Billion Transistors on a Fingernail
The scale of the achievement is staggering. IBM’s nanostack chip packs nearly 100 billion transistors onto an area the size of a fingernail — nearly twice the density of the company’s previous state-of-the-art 2nm technology announced in 2021. The key metrics:
- Node size: 0.7 nanometers (7 angstroms) — smaller than any previous chip technology
- Transistor count: ~100 billion on a fingernail-sized area
- Performance improvement: Up to 50% more work in the same time
- Energy efficiency: Up to 70% more efficient than IBM’s 2nm chips
- SRAM scaling: 40% improvement in memory density
To put the 0.7nm node in perspective: a human red blood cell is about 7,000 nanometers wide — roughly 10,000 times larger than one of these new transistor nodes. We are now engineering at scales approaching the size of individual atoms.
How the Technology Works
The nanostack architecture builds upon IBM’s nanosheet technology, which has been used to make state-of-the-art transistors since around 2022. A transistor is essentially a tiny switch through which electrons flow, with a valve that can turn the flow on or off. Inside the transistor, electrons move through a patch of silicon called a channel.
In IBM’s nanostack approach, the channel consists of three nanosheets that are each just 15 atoms thick, spaced nine nanometers apart. The critical innovation is that these transistors are stacked vertically and staggered — the transistors in the second layer do not sit directly on top of the first layer’s transistors, which simplifies wiring and provides other performance advantages.
The fabrication process is layered like a cake:
- First, transistors are fabricated on one layer of silicon
- A silicon layer is placed on top
- Another layer of transistors is fabricated directly on top of that
- Finally, electrical connections are created between the two layers
This type of vertical stack, which combines two types of transistors, is known as a complementary field-effect transistor, or CFET. IBM’s approach is distinguished by the staggered design, which the company says simplifies wiring compared to direct vertical stacking.
The Thermal Challenge
One of the most significant engineering challenges in creating the nanostack was what researchers call “the thermal budget.” Essentially, engineers needed to figure out how to build each layer without melting the connections to the one underneath. This requires keeping manufacturing processes below 400°C — a constraint that IBM’s team successfully addressed, though they have not disclosed their specific methods.
Qing Cao, a professor of materials science and engineering at the University of Illinois at Urbana-Champaign, who was not involved with the work, describes IBM’s approach as “transformative” because it demonstrates how to stack transistors “on a full wafer using a state-of-the-art manufacturing line.”
Impact on AI and Computing
The potential applications for nanostack technology are enormous, particularly in the field of artificial intelligence. IBM researchers estimate that an AI accelerator using 7 angstrom technology could deliver approximately 9,000 TOPS (trillions of operations per second) — roughly six times more than today’s popular AI accelerators, which produce about 1,500 TOPS.
If 7 angstrom chips were used to train today’s massive frontier AI models, the training time could potentially be cut from around three months to just a couple of weeks. This would dramatically accelerate the pace of AI development and reduce the enormous energy costs associated with training large language models.
The Race to Sub-1nm
IBM is not alone in pursuing advanced chip architectures. The biggest chip manufacturers — Intel, Samsung, and TSMC — and the competing research lab Imec in Belgium have all been investigating CFETs and related technologies. However, IBM’s nanostack architecture represents a significant lead in the race to sub-1nm technology.
Intel recently demonstrated its EMIB-T advanced packaging technology, which enables ultra-large die complexes with over 10x reticle dies and 12 Gb/s+ HBM4e DRAM. Samsung is accelerating its 2nm foundry strategy while also exploring quantum computing for chip design optimization. Meanwhile, a Chinese startup named Yuanjiwei has launched what it claims is the world’s first 8-inch production line for two-dimensional semiconductors, aiming to build 5nm equivalent chips without EUV lithography by 2029.
What This Means for the Industry
The announcement of nanostack technology has significant implications for multiple industries:
For semiconductor manufacturers: IBM’s nanostack provides a roadmap for continued scaling beyond the physical limits of traditional 2D approaches. The architecture is designed to be compatible with existing manufacturing infrastructure, making adoption more feasible.
For data center operators: The 70% energy efficiency improvement could translate into massive cost savings and reduced carbon footprints for the world’s data centers, which currently consume approximately 1-2% of global electricity.
For AI companies: The 50% performance improvement and 40% SRAM scaling gains could enable more powerful AI models and faster training times, accelerating the pace of AI development.
For consumers: While nanostack chips are still years away from consumer products, the technology could eventually lead to more powerful, energy-efficient smartphones, laptops, and other devices.
Timeline and Next Steps
IBM projects that nanostack technology could reach production in as early as the next five years. The company plans to partner with semiconductor manufacturers to produce actual chips, with the technology expected to be deployed across various chip types, including GPUs and CPUs.
The roadmap ahead includes further scaling to even smaller nodes, with IBM’s semiconductor roadmap projecting at least a decade of future scaling with the nanostack architecture. The company also recently announced plans to form Anderon, the world’s first pure-play quantum foundry, which will leverage both quantum computing and semiconductor expertise.
Conclusion
IBM’s nanostack architecture represents more than just an incremental improvement in chip technology — it represents a fundamental shift in how we think about transistor scaling. By moving from 2D to 3D, IBM has demonstrated that the semiconductor industry can continue to deliver performance and efficiency improvements for at least another decade, even as traditional approaches reach their physical limits. As the demands of AI, cloud computing, and other data-intensive applications continue to grow, innovations like nanostack will be essential to meeting the world’s computing needs.
